GENERATORS

ChipEDA provides several generators as part of the chipMason tool set These generators can be used as a stand alone applications or as part of the overall floorplanning.

We have worked with our customers to integrate chipMason generators with all major EDA vendors ASIC flow. They can be customized based on the specific needs of each customer.

dpMason™ - Data Path Generator

Most of the SoCs designed these days include one or more processors, they may include DSP or similar IP. All these blocks perform significant amount of data processing which implies they have signifant Data Path structures. Also, experience shows that even when the data path designers synthesize their logic the resulting layout may be disappointing. The area is not optimal nor is the speed satisfactory.


chipMason provider its users with a unique combination of high quality data path generator with very optimal layout Density.


The generated data path can be "merged" with the results of block to create a uniform layout space and will allow the PnR tools to place control logic in the middle of the generated data path improving the layout density as well as speed of the circuit.

rfMason™ - Register File Generator

One special case of data path generation is small memory arrays and register files. This approach uses standard cells as the basic building block to generate the memory structures improving the portability of the design.


chipMason rfGen can generate multiported (up to 3W6R) register files and memory arrays. The generator generates the logic netlist, layout placement and timing and layout abstracts.


Speed and area utilization rivals the results from best available on the market. The generated structures can be integrated seemlessly in the block floorplan.

ioMason™ - IO Generator

chipMason IO generator is a complete Package/Chip co-design system. It can start from a specification of the package with its pin assignment. It will check the routability of the package, assign the chip pads. It can be used to allocate the POWER/GROUND pads for the chip. It will generate placement of the PADS and IO Cells. The boundary scan logic can be generated by chipMason ioGen, as well as it can be used to trace and locate the Near Pad Logic (NPL). This feature is espacially important when designing high speed interfaces like DDR2. chipMason will generate PIN/PAD assignment used by the package manufactured to fully design and perform the final routing of the package. In addition, a top level floorplan is generated which includes all


If users prefer, they can start by designing their chip io-ring then use this placement of the PAD to help allocate PINS in the package.
chipMason supports wire bond as well as flip chip design.