CHIPMASON™

"chipMason" is a floorplanning and rapid silicon prototyping EDA toolset that supports package/chip co-design, hierarchical design flow and layout re-use methodology.

chipMason enables users to partition large designs and create accurate layout and timing abstracts and budgets. They can go from logic design view to a detailed floorplan with IO pads, power grid, block placement and pin assignment allowing them to quickly find and fix routing congestions as well as critical timing paths.

floorMason™ - hierarchical floorplanning with ReUse

Design ReUse is an essential part of chipMason features. Any block designed using chipMason can be reused multiple times in the same chip or it can be used in different chips.


The block is instrumented with repeater buffers and feed-through wires to allow easiers top level routing.
Pin assignment of the block is done with reusability in mind. Power is generated using chipMason to allow the block to be connected to the top level power grid without modifications, regardless of the structure of the top level power grid.


One of the biggest benefits of designing a reusable block, is the fact that the block can be designed concurrently and independently of the top level.

vRAute™ - Top Level Routing with repeater allocation

chipMason allows hierarchical partition and Re-Use methodologies and flows which enable users to efficiently tackle multi-million instance designs resulting in significant cost reduction and shorter time to market.

budgetMason™ - timing budgeting for hierarchical design

Users start using our floorplanning tool at the conceptual stage of their design. After the design is partitioned, each one of the hierarchical blocks is instrumented with repeater buffers. Virtual route is performed on the top level of the chip taking into account the routing congestion and the availability of repeater buffers.

Based on the initial block placement, and the initial virtual route, accurate top level wire delays are calculated and new accurate timing constaints for all the hierarchical blocks are generated.