ChipEDA is a provider of EDA tools and EDA services to IC design companies. By using our ChipMason(tm) family of tools and our proven technology, design teams are able to exploit the performance available in deep submicron geometries without incurring the usual productivity and schedule penalties.

Hierarchical design with ReUse methodology

ChipEDA has developed an innovative technology to allow their customers to partition their design into small, managable, hierarchical blocks which can be reused in the same chip or in different chips.

The hierarchical design approach has been promoted by many EDA suppliers. ChipEDA provide their customers with a unique technology, allowing them to achive their partitioning easily with the added benefit of being able to reuse their blocks multiple times in the same design or on different chips.

Designing a block with reusability in mind has another significant advantage even when the block is used only once in the same chip. Any block design using this approach allows the user to design all their hierarchical blocks and their top level simultanously, ensuring there is no dependency between the block level and top level.

Top level routing with flexible Repeater Insertion and allocation

As Part of the design partitioning, ChipMason performs initial routing of the top level blocks. This results in an accurate prediction of the interconnect and its impact on the blocks timing constrains.

• Fixed Repeaters Insertion in the hierachical blocks:


• Flexible Repeater Insertion in the top level:


• Top level Repeater Allocation utilizing all available repeater resource:


• Routing aware:


• Timing Aware:


• Porosity Aware:


• Signal Integrity:

ChipMason Technology

The basic foundation of ChipMason(tm) is high speed and capacity data base management software. ChipEDA has developed a unique technology that allows their customers to handle very big designs at speeds 3x-10x faster than comparable tools. All design views, like verilog gate netlist or layout def netlist, are read into ChipMason data base manager (dbmgr). Libraries, like LEF or LIB, are read into ChipMason's dbmgr as well. And finally, design properties, like timing contraints (sdc), Standard Delay Format (SDF) or Value Change Dump (VCD), are read into dbmgr.

The first SW layer to allow access to the data bases is provided through console. This API provides cw fast access to the underlying data base.

• vconsole: gatelevel netlist (verilog format) manipulator
• pdconsole: physical design netlist (lef/def format) manipulator
• tbconsole: timing and budgeting (lib/sdc format) calculator.

In addtion and on top of the consoles, ChipMason provides the user with high level interface to browse and edit the data base:

• vEditor: allows the users to edit or browse their gatelevel netlist
• pdEditor: allows the users to edit or browse their physical design
• tBrowser: is a fast Statis Timing Analyzer (STA), it allows the users to trace and browse their designs taking into account the timing information and constraints

Netlisting Technology

ChipMason's vEditor allows the user to read verilog netlists of big designs in few minutes - ~50 million instance in 3 minutes- It allows the user to browse and edit the design to perform operations like: grouping, ungrouping, flattening, logic cloning and many other operations that are needed to prepare the design for the physical design phase. ChipMason verilog netlisting engine is "foregiving", meaning that it will not stop on the first parsing error, and will continue as long as possible. This feature allows the user to start their physical design activity even when the logical netlist is not stable yet.

ChipMason's pdEditor allows the user to create or read physical designs. It is used for floorplanning, which include block creation, pins assignment and power grid generations.

For more details, please refer to ChipMason documentations.

Timing Analysis Technology

Our partition and Re-Use methodology and flow enable multi-million instance designs to be tackled efficiently augmenting design teams' existing EDA tools which results in significant cost reduction and shorter time to market.