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ChipEDA joins MagmaTies program. As part of Magma partners program, we will integrate our ChipEDA tool with Magma tools and flows focusing on two main areas, top level chip integration and data path generation.
 
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Item Title Hits
Using VEditor to extract connectivity information 740
Dealing with incomplete netlists 840
How to iterate across the module definitions and module items. 725
Check for correct physical connectivity 798
How assigns can be translated into a buffer of choice using the HwMapper 767
How assigns can be translated into wires 813
Flattening operation on a netlist 881
Generating a report for a design using hierReport 838
Performing a global rename operation 772
Example of hierarchical write out options 761
Read in same netlist in multiple designs 797
Basic flattening operation on a netlist 930
How to reduce the netlist size 832
Using ecoEditor functions, to connect pins togheter. 774
Using ecoEditor functions, to disconnect pins of the instance 746
Debussifying an entire netlist 905
How to create a stub for a verilog 922
Using VEditor to extract connectivity information 828
Using VEditor to report all counts and estimated cell area 867
Reading in a library and a Verilog netlist 927
How to use pdDisplay ? 844
How to compare two designs with ncomp ? 787
How to read in two different libraries and use the tool to compare the equivalent library cells. 892
How to read in a library and use writeLiberty to save the library and add cells' name prefix 849
How to read in a library, compile and save it 915
How to convert library to verilog stubs? 1092
How to analyze a new library 999
How do I download ChipMason 933
What is "ChipMason" 996
 
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