ChipEDA is a provider of EDA tools and EDA integration services to IC design companies. By using our ChipMason™ family of tools and our proven technology, design teams are able to exploit the performance available in deep submicron geometries without incurring the usual productivity and schedule penalties. ChipEDA's focus is to improve key aspects of the design flow such as hand-off between the logical and physical phases and hierarchical design issues. ChipMason is a complete SoC floor planning tool. It automates the block/macro placement, pin placement and power grid generation. ChipMason can be integrated with any generic P&R tool. ChipMason is most distinguished for chip level integration of hierarchical SoC, utilizing our unique "vRAute™" technology. It allows top level routing through the hierarchical blocks utilizing routing channels reserved in these blocks and utilizing repeaters already inserted in these blocks to buffer long nets while optimizing wire length. This unique feature gives our customers the ability to design re-usable blocks and to separate block level from top level design work giving them significant benefits: - shorter schedule
- reduced engineering cost
ChipMason combined with our partition and Re-Use methodology/flows enable multi-million instance designs to be tackled efficiently augmenting design teams' existing EDA tools which results in significant cost reduction and shorter time to market.  Please see white papers from ChipEDA :
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Azul Systems Selects ChipMason |
Azul Systems Selects ChipMason™ EDA tool and its vRAute™ Global Route Technology to Integrate its State of the Art 90nm 48 Core Vega2™ Processor SAN JOSE, Calif., Nov 14, 2006 (BUSINESS WIRE) -- ChipEDA, a provider of EDA tools and services, today announced that Azul Systems, a global provider of enterprise server appliances, licensed the ChipMason Design Flow and its vRAute(tm) technology to integrate its state of the art 48 core, Vega(tm) 2 processor. Azul announced the industry's largest multicore chip was in their labs back in March 2006 (http://www.azulsystems.com/press/032706_vega2.htm) "By selecting ChipEDA's hierarchical design flow, we were able to achieve design closure while cutting implementation costs significantly," said Paul Koike, Sr. Director, Silicon Engineering at Azul Systems. "ChipEDA's hierarchical layout re-use flow in conjunction with their global route capability, made the problem of integrating a very large chip, with aggressive timing goals manageable by a small design team, allowing us to achieve timing closure." "ChipEDA's hierarchical design flow with built in timing closure and layout re-use enables our customers to build an entire product line around a core technology in record time with minimal resources. By adopting ChipMason, Azul Systems was able to increase their functionality on chip and their timing goals, while keeping design costs and schedule under control," said Fuad Abu Nofal (Founder and Principal Engineer). About Azul Systems Azul Systems is a global provider of enterprise server appliances that delivers compute and memory resources as a shared network service for transaction-intensive applications, such as those built on the Java(tm) platform. Our family of Azul Compute Appliances enables transparent, massively scalable infrastructure that supports the business priorities of today's most demanding enterprise environments and delivers increased capabilities, capacity and utilization at a fraction of the cost of traditional computing models. About ChipEDA "ChipEDA" is a provider of EDA tools and services for chip floor planning and rapid silicon prototyping. "ChipMason" EDA tool set, supports package/chip co-design, hierarchical design flow and layout re-use methodology. Design ReUse is an essential part of the ChipMason feature set. Any block designed using ChipMason can be reused multiple times in the same chip or across multiple chips. Pin assignment of the block is done with reusability in mind. Through its unique global route technology vRAute, ChipMason allows designers to plan upfront the buffering of their global wires and to route/time the top level of the chip while the underlying blocks are still under construction. Thanks to a "correct by construction" approach, this methodology solves the design issues of global timing convergence and layout reuse. Power is generated using ChipMason to allow the block to be connected to the top level power grid without modifications, regardless of the structure of the top level power grid. ChipMason users tackle multi-million instance designs efficiently and gain significant cost reduction in their product development and shorter time to market. www.chipeda.com |
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C2 Microsystems Selects ChipMason |
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C2 Microsystems, Inc. and ChipEDA announced today that C2Micro extends their use of ChipMason tools set from ChipEDA. SAN JOSE, CALIF. Jan 29, 2007 - C2 Microsystems, Inc. and ChipEDA announced today their plans to extend their collaboration designing C2Micro next generation chips using ChipMason EDA tool set. C2 Micro will use ChipMason for floorplanning and data path generation.
C2micro is the leading developer of fully programmable media processors for low cost, high performance and networked media. It designed a family of high performance and high integration SoC, and rich I/O interfaces. C2 micro SoC's are targeting low cost, high performance audio/video applications such as IP STB, Portable Media Player/Recorder, hard disk Personal Video Recorder, network Personal Video Recorder, and Digital Media Adapter.
"We have used ChipMason(tm) to perform the floorplanning of our first generation SoC and we are pleased with the results" said Jinxiang (Gene) Liu, Ph.D., President and CEO of C2 Microsystems, "ChipEDA floorMason(tm), used for floorplanning, helped us improve the layout efficiency of our SoC. In addition, we used extensively the ChipEDA data path generation".
"Our markets require us to produce high performance chips while keeping their cost at minimum. By using floorMason with its advanced hierarchical floorplanning capabilities, we are able to automate the chip floorplanning phase" continued Dr. Liu , "Using ChipEDA's data path generation, dpMason(tm), we achieved very high layout density for our media processor. The high density and the special features used to lower the power consumption are essential for our targeted markets.
"We are pleased about our previous engagement with C2 Microsystems and are happy to see our joint efforts yield the expected results" said Monica Nofal, President and CEO of ChipEDA. "By using the advanced floor planning features of ChipMason, our tool can partition complex SoCs into manageable blocks, allowing layout re-use and rapid timing closure.
"By using dpMason, our customers get layout densities over 95%, reduce the power consumption of their chips and achieve their cost targets" continued Ms. Nofal, "Our customer can use the tool build-in functions to generate data path elements. These functions can be extended by the user as well. dpMason uses Industry standard interfaces allowing the customers to integrate our tool with their ASIC flow"
About C2 Microsystems
Inc. C2 Microsystems, Inc. was founded by a group of veteran Silicon Valley entrepreneurs in May, 2004 with the target to create the best technology in the world for digital home and mobile entertainment. C2Micro is developing a family of low-cost, high performance, fully programmable SOCs which includes an integrated software development environment that is optimized for networked media from portable to high definition applications. C2's unique approach to media processing involves a blend of hardware and software implementation of all major audio and video codecs and an application framework that allows programmers total control of media applications: any codec, any quality, any resolution, any time and anywhere. For more information, visit C2 Micro online at http://www.c2micro.com.
About ChipEDA
"ChipEDA" is a provider of EDA tools chip floor planning and rapid silicon prototyping. "ChipMason" EDA tool set, supports package/chip co-design, hierarchical design flow and layout re-use methodology. Design ReUse is an essential part of the ChipMason feature set. Any block designed using ChipMason can be reused multiple times in the same chip or across multiple chips. Pin assignment of the block is done with reusability in mind. Through its unique global route technology vRAute, ChipMason allows designers to plan upfront the buffering of their global wires and to route/time the top level of the chip while the underlying blocks are still under construction. Thanks to a "correct by construction" approach, this methodology solves the design issues of global timing convergence and layout reuse.Power is generated using ChipMason to allow the block to be connected to the top level power grid without modifications, regardless of the structure of the top level power grid. ChipMason users tackle multi-million instance designs efficiently and gain significant cost reduction in their product development and shorter time to market. For more information visit http://www.chipeda.com |
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